| 000 | 02915naaaa2200265uu 4500 | ||
|---|---|---|---|
| 001 | https://directory.doabooks.org/handle/20.500.12854/50409 | ||
| 005 | 20220220051322.0 | ||
| 020 | _a/doi.org/10.1007/978-1-4302-5927-5 | ||
| 020 | _a9781430259275 | ||
| 020 | _a9781430259268 | ||
| 024 | 7 |
_ahttps://doi.org/10.1007/978-1-4302-5927-5 _cdoi |
|
| 041 | 0 | _aEnglish | |
| 042 | _adc | ||
| 100 | 1 |
_aRezaur Rahman _4auth |
|
| 245 | 1 | 0 | _aIntel Xeon Phi Coprocessor Architecture and Tools: The Guide for Application Developers |
| 260 |
_bApress _c2013 |
||
| 300 | _a1 electronic resource (232 p.) | ||
| 506 | 0 |
_aOpen Access _2star _fUnrestricted online access |
|
| 520 | _aIntel® Xeon Phi™ Coprocessor Architecture and Tools: The Guide for Application Developers provides developers a comprehensive introduction and in-depth look at the Intel Xeon Phi coprocessor architecture and the corresponding parallel data structure tools and algorithms used in the various technical computing applications for which it is suitable. It also examines the source code-level optimizations that can be performed to exploit the powerful features of the processor. Xeon Phi is at the heart of world’s fastest commercial supercomputer, which thanks to the massively parallel computing capabilities of Intel Xeon Phi processors coupled with Xeon Phi coprocessors attained 33.86 teraflops of benchmark performance in 2013. Extracting such stellar performance in real-world applications requires a sophisticated understanding of the complex interaction among hardware components, Xeon Phi cores, and the applications running on them. In this book, Rezaur Rahman, an Intel leader in the development of the Xeon Phi coprocessor and the optimization of its applications, presents and details all the features of Xeon Phi core design that are relevant to the practice of application developers, such as its vector units, hardware multithreading, cache hierarchy, and host-to-coprocessor communication channels. Building on this foundation, he shows developers how to solve real-world technical computing problems by selecting, deploying, and optimizing the available algorithms and data structure alternatives matching Xeon Phi’s hardware characteristics. From Rahman’s practical descriptions and extensive code examples, the reader will gain a working knowledge of the Xeon Phi vector instruction set and the Xeon Phi microarchitecture whereby cores execute 512-bit instruction streams in parallel. | ||
| 536 | _aIntel | ||
| 540 |
_aCreative Commons _fhttps://creativecommons.org/licenses/by-nc-nd/4.0/ _2cc _4https://creativecommons.org/licenses/by-nc-nd/4.0/ |
||
| 546 | _aEnglish | ||
| 856 | 4 | 0 |
_awww.oapen.org _uhttps://link.springer.com/book/10.1007/978-1-4302-5927-5 _70 _zDOAB: download the publication |
| 856 | 4 | 0 |
_awww.oapen.org _uhttps://directory.doabooks.org/handle/20.500.12854/50409 _70 _zDOAB: description of the publication |
| 999 |
_c67207 _d67207 |
||