Miniaturized Transistors
Grasser, Tibor
Miniaturized Transistors - MDPI - Multidisciplinary Digital Publishing Institute 2019 - 1 electronic resource (202 p.)
Open Access
What is the future of CMOS? Sustaining increased transistor densities along the path of Moore's Law has become increasingly challenging with limited power budgets, interconnect bandwidths, and fabrication capabilities. In the last decade alone, transistors have undergone significant design makeovers; from planar transistors of ten years ago, technological advancements have accelerated to today's FinFETs, which hardly resemble their bulky ancestors. FinFETs could potentially take us to the 5-nm node, but what comes after it? From gate-all-around devices to single electron transistors and two-dimensional semiconductors, a torrent of research is being carried out in order to design the next transistor generation, engineer the optimal materials, improve the fabrication technology, and properly model future devices. We invite insight from investigators and scientists in the field to showcase their work in this Special Issue with research papers, short communications, and review articles that focus on trends in micro- and nanotechnology from fundamental research to applications.
Creative Commons
English
books978-3-03921-011-4 9783039210107 9783039210114
10.3390/books978-3-03921-011-4 doi
MOSFET n/a total ionizing dose (TID) low power consumption process simulation two-dimensional material negative-capacitance power consumption technology computer aided design (TCAD) thin-film transistors (TFTs) band-to-band tunneling (BTBT) nanowires inversion channel metal oxide semiconductor field effect transistor (MOSFET) spike-timing-dependent plasticity (STDP) field effect transistor segregation systematic variations Sentaurus TCAD indium selenide nanosheets technology computer-aided design (TCAD) high-? dielectric subthreshold bias range statistical variations fin field effect transistor (FinFET) compact models non-equilibrium Green’s function etching simulation highly miniaturized transistor structure compact model silicon nanowire surface potential Silicon-Germanium source/drain (SiGe S/D) nanowire plasma-aided molecular beam epitaxy (MBE) phonon scattering mobility silicon-on-insulator drain engineered device simulation variability semi-floating gate synaptic transistor neuromorphic system theoretical model CMOS ferroelectrics tunnel field-effect transistor (TFET) SiGe metal gate granularity buried channel ON-state bulk NMOS devices ambipolar piezoelectrics tunnel field effect transistor (TFET) FinFETs polarization field-effect transistor line edge roughness random discrete dopants radiation hardened by design (RHBD) low energy flux calculation doping incorporation low voltage topography simulation MOS devices low-frequency noise high-k layout level set process variations subthreshold metal gate stack electrostatic discharge (ESD)
Miniaturized Transistors - MDPI - Multidisciplinary Digital Publishing Institute 2019 - 1 electronic resource (202 p.)
Open Access
What is the future of CMOS? Sustaining increased transistor densities along the path of Moore's Law has become increasingly challenging with limited power budgets, interconnect bandwidths, and fabrication capabilities. In the last decade alone, transistors have undergone significant design makeovers; from planar transistors of ten years ago, technological advancements have accelerated to today's FinFETs, which hardly resemble their bulky ancestors. FinFETs could potentially take us to the 5-nm node, but what comes after it? From gate-all-around devices to single electron transistors and two-dimensional semiconductors, a torrent of research is being carried out in order to design the next transistor generation, engineer the optimal materials, improve the fabrication technology, and properly model future devices. We invite insight from investigators and scientists in the field to showcase their work in this Special Issue with research papers, short communications, and review articles that focus on trends in micro- and nanotechnology from fundamental research to applications.
Creative Commons
English
books978-3-03921-011-4 9783039210107 9783039210114
10.3390/books978-3-03921-011-4 doi
MOSFET n/a total ionizing dose (TID) low power consumption process simulation two-dimensional material negative-capacitance power consumption technology computer aided design (TCAD) thin-film transistors (TFTs) band-to-band tunneling (BTBT) nanowires inversion channel metal oxide semiconductor field effect transistor (MOSFET) spike-timing-dependent plasticity (STDP) field effect transistor segregation systematic variations Sentaurus TCAD indium selenide nanosheets technology computer-aided design (TCAD) high-? dielectric subthreshold bias range statistical variations fin field effect transistor (FinFET) compact models non-equilibrium Green’s function etching simulation highly miniaturized transistor structure compact model silicon nanowire surface potential Silicon-Germanium source/drain (SiGe S/D) nanowire plasma-aided molecular beam epitaxy (MBE) phonon scattering mobility silicon-on-insulator drain engineered device simulation variability semi-floating gate synaptic transistor neuromorphic system theoretical model CMOS ferroelectrics tunnel field-effect transistor (TFET) SiGe metal gate granularity buried channel ON-state bulk NMOS devices ambipolar piezoelectrics tunnel field effect transistor (TFET) FinFETs polarization field-effect transistor line edge roughness random discrete dopants radiation hardened by design (RHBD) low energy flux calculation doping incorporation low voltage topography simulation MOS devices low-frequency noise high-k layout level set process variations subthreshold metal gate stack electrostatic discharge (ESD)